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| IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST COMMERCIAL TEMPERATURE RANGE 1.8V CONFIGURABLE BUFFER WITH ADDRESSPARITY TEST FEATURES: * * * * * * * * * * * * IDT74SSTUA32866 1.8V Operation SSTL_18 style clock and data inputs Differential CLK input Configurable as 25-bit 1:1 or 14-bit 1:2 registered buffer Control inputs compatible with LVCMOS levels Flow-through architecture for optimum PCB design Latch-up performance exceeds 100mA ESD >2000V per MIL-STD-883, Method 3015; >200V using machine model (C = 200pF, R = 0) Checks parity on data inputs Maximum operating frequency: 410MHz Optimized for DDR2 - 400 / 533 / 667 (PC2 - 3200 / 4300 / 5300) JEDEC R/C E, F, G, H, and J Available in 96-pin LFBGA package APPLICATIONS: * Along with CSPUA877 DDR2 PLL, provides complete solution for DDR2 DIMMs DESCRIPTION: This 25-bit 1:1 / 14-bit 1:2 configurable registered buffer is designed for 1.7V to 1.9V VDD operation. In the 1:1 pinout configuration, only one device per DIMM is requred to drive nine SDRAM loads. In the 1:2 pinout configuration, two devices per DIMM are required to drive eighteen SDRAM loads. All inputs are SSTL_18, except reset (RESET) and control (Cn) inputs, which are LVCMOS. All outputs are edge-controlled circuits optimized for unterminated DIMM loads, and meet SSTL_18 specifications, except the open-drain error (QERR) output. The SSTUA32866 operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK going low. Parity is checked on the parity bit (PAR_IN) input which arrives one cycle after the input data to which it applies. The QERR output is open drain. When used as a single device, the C0 and C1 inputs are tied low. In this configuration, the partial-parity-out (PPO) and QERR signals are produced two clock cycles after the corresponding data output. When used in pairs, the C0 input of the first register is tied low and the C0 input of the second register is tied high. The C1 input of both registers are tied high. The QERR output of the first SSTUA32866 is left floating and the valid error information is latched on the QERR output of the second SSTUA32866. If an error occurs and the QERR output is driven low, it stays latched low for two clock cycles or until RESET is driven low. The DIMM-dependent signals (DODT, DCKE, DCS, and CSR) are not included in the parity check. The CO input controls the pinout configuration of the 1:2 pinout from register A configuration (when low) to register B configuration (when high). The C1 input controls the pinout configurationfrom 25-bit 1:1 (when low) to 14-bit 1:2 (when high). C0 and C1 should not be switched during normal operation. They should be hard-wired to a valid low or high level to configure the register in the desired mode. In the 25-bit 1:1 pinout configuration, the A6, D6, and H6 terminals are driven low and should not be used. The device supports low-power standby operation. When RESET is low, the differential input recievers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET is low, all registers are reset and all outputs except QERR are forced low. The LVCMOS RESET and Cn inputs always must be held at a valid logic high or low level. There are two VREF pins (A3 and T3). However, it is necessary to only connect one of the two VREF pins to the external VREF power supply. An unused VREF pin should be terminated with a VREF coupling capacitor. The device also supports low-power active operation by monitoring both system chip select (DCS and CSR) inputs and will gate the Qn and PPO outputs from changing states when both DCS and CSR inputs are high. If either DCS or CSR input is low, the Qn and PPO outputs will function normally. Also, if the internal low power signal (LPS1) is high, the device will gate the QERR output from changing states. If LPS1 is low, the QERR output will function normally. The RESET input has priority over the DCS and CSR control and when driven low will force the Qn and PPO outputs low, and the QERR output high. If the DCS control functionality is not desired, then the CSR input can be hard-wired to ground, in which case the setuptime requirement for DCS would be the same as for the other D data inputs. To control the low-power mode with DCS only, then the CSR input should be pulled up to VDD through a pullup resistor. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up. COMMERCIAL TEMPERATURE RANGE 1 c 2005 Integrated Device Technology, Inc. The IDT logo is a registered trademark of Integrated Device Technology, Inc. JUNE 2005 DSC 6382/9 IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST COMMERCIAL TEMPERATURE RANGE FUNCTIONAL BLOCK DIAGRAM (1:2) - A CONFIGURATION (POSITIVE LOGIC) RESET CLK CLK VREF DCKE 1D C1 R QCKEA QCKEB DODT 1D C1 R QODTA QODTB DCS 1D C1 R QCSA QCSB CSR D2 0 1 1D C1 R Q2B Q2A One of 11 Channels TO 10 OTHER CHANNELS (D3, D5, D6, D8-D14) 2 IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST COMMERCIAL TEMPERATURE RANGE FUNCTIONAL BLOCK DIAGRAM (1:2) - B CONFIGURATION (POSITIVE LOGIC) RESET CLK CLK VREF DCKE 1D C1 R QCKEA QCKEB DODT 1D C1 R QODTA QODTB DCS 1D C1 R QCSA QCSB CSR D1 0 1 1D C1 R Q1B Q1A One of 11 Channels TO 10 OTHER CHANNELS (D2-D6, D8-D10, D12-D13) 3 IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST COMMERCIAL TEMPERATURE RANGE PIN CONFIGURATION (TYPE A) NC Q12B 6 QCKEB Q2B Q3B QODTB Q5B Q6B C0 QCSB Q8B Q9B Q10B Q11B Q13B Q14B 5 QCKEA Q2A Q3A QODTA Q5A Q6A C1 QCSA NC Q8A Q9A Q10A Q11A Q12A Q13A Q14A 4 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VDD 3 VREF GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VREF 2 PPO DNU DNU QERR DNU DNU RESET DCS CSR DNU DNU DNU DNU DNU DNU DNU 1 DCKE D2 D3 DODT D5 D6 PAR_IN CLK CLK D8 D9 D10 D11 D12 D13 D14 A B C D E F G H J K L M N P R T 96-PIN LFBGA 1:2 REGISTER (TYPE A, FRONTSIDE) TOP VIEW PIN CONFIGURATION (TYPE B) 6 Q1B Q2B Q3B Q4B Q5B Q6B C0 QCSB NC Q8B Q9B Q10B QODTB Q12B Q13B QCKEB 5 Q1A Q2A Q3A Q4A Q5A Q6A C1 QCSA NC Q8A Q9A Q10A QODTA Q12A Q13A QCKEA 4 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VDD 3 VREF GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VREF 2 PPO DNU DNU QERR DNU DNU RESET DCS CSR DNU DNU DNU DNU DNU DNU DNU 1 D1 D2 D3 D4 D5 D6 PAR_IN CLK CLK D8 D9 D10 DODT D12 D13 DCKE A B C D E F G H J K L M N P R T 96-PIN LFBGA 1:2 REGISTER (TYPE B, BACKSIDE) TOP VIEW 4 IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST COMMERCIAL TEMPERATURE RANGE FUNCTIONAL BLOCK DIAGRAM (1:1) RESET CLK1 CLK1 VREF DCKE 1D C1 R QCKE DODT 1D C1 R QOTD DCS 1D C1 R QCS CSR D2 0 1 1D C1 R Q2 One of 22 Channels TO 21 OTHER CHANNELS (D3, D5, D6, D8-D25) 5 IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST COMMERCIAL TEMPERATURE RANGE PIN CONFIGURATION 6 DNU Q15 Q16 DNU Q17 Q18 C0 DNU NC Q19 Q20 Q21 Q22 Q23 Q24 Q25 5 QCKE Q2 Q3 QODT Q5 Q6 C1 QCS NC Q8 Q9 Q10 Q11 Q12 Q13 Q14 4 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VDD 3 VREF GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VREF 2 PPO D15 D16 QERR D17 D18 RESET DCS CSR D19 D20 D21 D22 D23 D24 D25 1 DCKE D2 D3 DODT D5 D6 PAR_IN CLK CLK D8 D9 D10 D11 D12 D13 D14 A B C D E F G H J K L M N P R T *Rows 3 and 4 are reserved for VDD and GND. 96-PIN LFBGA 1:1 REGISTER TOP VIEW 96 BALL LFBGA PACKAGE ATTRIBUTES 6 5 4 3 2 1 A Top Marking B C D E F G H J K L M N P R T TOP VIEW A B C D E F G H J K L M N P R T 1 2 3 4 5 6 BOTTOM VIEW 6 SIDE VIEW IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST COMMERCIAL TEMPERATURE RANGE FUNCTION TABLE (EACH FLIP-FLOP) (1) Inputs RESET H H H H H H H H H H H H L DCS L L L L L L H H H H H H X or Floating CSR L L L H H H L L L H H H X or Floating CLK L or H L or H L or H L or H X or Floating CLK L or H L or H L or H L or H X or Floating Dx, DODT, DCKE L H X L H X L H X L H X X or Floating Qx Outputs L H Q0 (2) QCSx Output L L Q0 (2) QODTx, QCKEx Outputs L H Q0(2) L H Q0(2) L H Q0(2) L H Q0(2) L L H Q0 (2) L L Q0 (2) L H Q0(2) Q0(2) Q0 (2) H H Q0(2) H H Q0(2) L Q0(2) L NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care = LOW to HIGH = HIGH to LOW 2. Output level before the indicated steady-state conditions were established. PARITY AND STANDBY FUNCTION TABLE(1) Inputs RESET H H H H H H H H H H L DCS L L L L H H H H H X X or Floating CSR X X X X L L L L H X X or Floating CLK L or H X or Floating CLK L or H X or Floating of Inputs = H (D1 - D25) Even Odd Even Odd Even Odd Even Odd X X X or Floating PAR_IN(2) L L H H L L H H X X X or Floating PPO(3) L H H L L H H L PPO 0 PPO 0 L Outputs QERR(4) H L L H H L L H QERR0 QERR0 H NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care = LOW to HIGH = HIGH to LOW 2. Data Inputs = D2, D3, D5, D6, D8 - D25 when C0 = 0 and C1 = 0. Data Inputs = D2, D3, D5, D6, D8 - D14 when C0 = 0 and C1 = 1. Data Inputs = D1 - D6, D8 - D10, D12, D13 when C0 = 1 and C1 = 1. 3. PAR_IN arrives one clock cycle (C0 = 0), or two clock cycles (C0 = 1), after the data to which it applies. 4. This transition assumes QERR is HIGH at the crossing of CLK going HIGH and CLK going LOW. If QERR is LOW, it stays latched LOW for two clock cycles or until RESET is driven LOW. 7 IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST COMMERCIAL TEMPERATURE RANGE LOGIC DIAGRAM (1:1) G2 RESET H1 J1 CLK CLK D2 - D3, D5 - D6, D8 - D25 VREF LPS0 (Internal Node) 22 A3, T3 D CE CE CLK 22 D2 - D3, D5 - D6, D8 - D25 22 Q2 - Q3, Q5 - Q6, Q8 - Q25 R 22 D2 - D3, D5 - D6, D8 - D25 Parity Check C1 G5 0 D CLK R G1 1 D CLK R CE D CLK R A2 PPO 1 0 PAR_IN D2 QERR C0 G6 CLK 2-Bit Counter R LPS1 (Internal Node) 0 D 1 CLK R Parity Logic Diagram for 1:1 Register - A Configuration (Positive Logic); C0 = 0, C1 = 0 8 IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST COMMERCIAL TEMPERATURE RANGE LOGIC DIAGRAM (1:2) G2 RESET H1 J1 CLK CLK D2 - D3, D5 - D6, D8 - D14 VREF LPS0 (Internal Node) 11 A3, T3 D CE CE CLK 11 D2 - D3, D5 - D6, D8 - D14 11 Q2A - Q3A, Q5A - Q6A, Q8A - Q14A Q2B - Q3B, Q5B - Q6B, Q8B - Q14B 11 R 11 D2 - D3, D5 - D6, D8 - D14 Parity Check C1 G5 0 D CLK R G1 1 D CLK R CE D CLK R A2 PPO 1 0 PAR_IN D2 QERR C0 G6 CLK 2-Bit Counter R LPS1 (Internal Node) 0 D 1 CLK R Parity Logic Diagram for 1:2 Register - A Configuration (Positive Logic); C0 = 0, C1 = 1 9 IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS (1) Symbol VDD VI (2,3) MODE SELECT Unit V V V mA mA mA mA C C0 0 0 1 1 C1 0 1 0 1 Device Mode 1:1 25-bit to 25-bit 1:2 14-bit to 28-bit, Front (Type A) Reserved 1:2 14-bit to 28-bit, Back (Type B) Description Supply Voltage Range Input Voltage Range Output Voltage Range Input Clamp Current VI < 0 VI > VDD Max. -0.5 to 2.5 -0.5 to 2.5 -0.5 to VDD +0.5 50 50 50 100 -65 to +150 VO(2,3) IIK IOK IO VDD TSTG Output Clamp Current VO < 0 VO > VDD Continuous Output Current, VO = 0 to VDD Continuous Current through each VDD or GND Storage Temperature Range NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. The input and output negative voltage ratings may be exceeded if the ratings of the I/P and O/P clamp current are observed. 3. This value is limited to 2.5V maximum. TERMINAL FUNCTIONS (ALL PINS) Terminal Name GND VDD VREF CLK CLK Cx RESET CSR, DCS Dx DODT DCKE Qx QCSx QODTx QCKEx PAR_IN QERR PPO Electrical Characteristics Ground Input 1.8V nominal 0.9V nominal Differential Input Differential Input LVCMOS Input LVCMOS Input SSTL_18 Input SSTL_18 Input SSTL_18 Input SSTL_18 Input 1.8V CMOS 1.8V CMOS 1.8V CMOS 1.8V CMOS SSTL_18 Input Open Drain Output 1.8V CMOS Description Ground Power Supply Voltage Input Reference Voltage Positive Master Clock Input Negative Master Clock Input Configuration Control Inputs Asynchronous Reset Input. Resets registers and disables VREF data and clock differential-input receivers. Chip Select Inputs. Disables outputs Dx switching when both inputs are HIGH. Data Input. Clocked in on the crossing of the rising edge of CLK and the falling edge of CLK. The outputs of this register bit will not be suspended by the DCS and CSR controls The outputs of this register bit will not be suspended by the DCS and CSR controls Data Outputs that are suspended by the DCS and CSR controls Data Output that will not be suspended by the DCS and CSR controls Data Output that will not be suspended by the DCS and CSR controls Data Output that will not be suspended by the DCS and CSR controls Parity Input. Clocked on the rising edge of CLK one cycle after corresponding data input. Output Error bit, generated one cycle after the corresponding data output Partial Parity Output. Indicates ODD parity of Data Inputs and Parity In. 10 IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST COMMERCIAL TEMPERATURE RANGE OPERATING CHARACTERISTICS, TA = 25C (1,2) Symbol VDD VREF VTT VI VIH VIL VIH VIL VIH VIL VICR VID IOH IOL TA Parameter Supply Voltage Reference Voltage Termination Voltage Input Voltage AC High-Level Input Voltage AC Low-Level Input Voltage DC High-Level Input Voltage DC Low-Level Input Voltage High-Level Input Voltage Low-Level Input Voltage Common Mode Input Voltage Differential Input Voltage High-Level Output Current Low-Level Output Current Operating Free-Air Temperature RESET, Cx RESET, Cx CLK, CLK CLK, CLK Data Outputs, PPO Data Outputs, PPO, QERR Data Inputs, CSR, DCS, PAR_IN Min. 1.7 0.49 * VDD VREF- 40mV 0 VREF+ 250mV -- VREF+ 125mV -- 0.65 * VDD -- 0.675 600 -- -- 0 Typ. -- 0.5 * VDD VREF -- -- -- -- -- -- -- -- -- -- -- -- Max. 1.9 0.51 * VDD VREF+ 40mV VDD -- VREF- 250mV -- VREF- 125mV -- 0.35 * VDD 1.125 -- -8 8 70 C V V V mV mA V Unit V V V V NOTES: 1. The RESET and Cx inputs of the device must be held at valid levels (not floating) to ensure proper device operation. 2. The differential inputs must not be floating unless RESET is LOW. DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0C to +70C, VDD = 1.8V 0.1V Symbol VOH VOL II IDD IDDD Parameter Output HIGH Voltage Output LOW Voltage All Inputs (1) Test Conditions IOH = -6 mA IOL = 6 mA VI = VDD or GND; VDD = 1.9V IO = 0, VDD = 1.9V, RESET = GND IO = 0, VDD = 1.9V, RESET = VDD, VI = VIH (AC) or VIL (AC) IO = 0, VDD = 1.8V, RESET = VDD, VI = VIH (AC) or VIL (AC), CLK and CLK Switching 50% Duty Cycle. IO = 0, VDD = 1.8V, RESET = VDD, 1:1 Mode 1:2 Mode Min. 1.2 -- -- -- -- -- -- -- 2.5 Typ. -- -- -- -- -- -- -- -- -- -- -- Max. -- 0.5 5 100 40 -- -- Unit V V A A mA A/Clock MHz A/Clock Static Standby Static Operating Dynamic Operating (Clock Only) Dynamic Operating (Per Each Data Input) Data Inputs, CSR, PAR_IN VI = VIH (AC) or VIL (AC), CLK and CLK Switching at 50% Duty Cycle. One Data Input Switching at Half Clock Frequency, 50% Duty Cycle. 3.5 3 -- -- MHz/Data Input CI CLK and CLK RESET VICR = 0.9V, VID = 600mV VI = VDD or GND 2 -- pF NOTE: 1. Each VREF pin (A3, T3) should be tested independently, with the other pin open circuit. 11 IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST COMMERCIAL TEMPERATURE RANGE TIMING REQUIREMENTS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE VDD = 1.8V 0.1V Symbol fCLOCK tw tACT(1,2) tINACT(1,3) tSU Parameter Clock Frequency Pulse Duration, CLK, CLK HIGH or LOW Differential Inputs Active Time Differential Inputs Inactive Time DCS before CLK, CLK, CSR HIGH; CSR before CLK, CLK, DCS HIGH Setup Time DCS before CLK, CLK, CSR LOW DODT, DCKE, and data before CLK, CLK PAR_IN before CLK, CLK tH Hold Time DCS , DODT, DCKE, and data after CLK, CLK PAR_IN after CLK, CLK NOTES: 1. This parameter is not production tested. 2. Data and VREF inputs must be low a minimum time of tACT max, after RESET is taken HIGH. 3. Data, VREF, and clock inputs must be held at valid levels (not floating) a minimum time of tINACT max, after RESET is taken LOW. Min. -- 1 -- -- 0.7 0.5 0.5 0.5 0.5 0.5 Max. 410 -- 10 15 -- -- -- -- -- -- Unit MHz ns ns ns ns ns SWITCHING CHARACTERISTICS OVER RECOMMENDED FREE-AIR OPERATING RANGE (UNLESS OTHERWISE NOTED) (1) VDD = 1.8V 0.1V Symbol fMAX tPDM(2) tPDMSS(2,3) tRPHL dV/dt_r dV/dt_f dV/dt_(4) tPD tPLH tPHL tRPHL tRPLH CLK and CLK to Q CLK and CLK to Q (simultaneous switching) RESET to Q Output slew rate from 20% to 80% Output slew rate from 20% to 80% Output slew rate from 20% to 80% CLK and CLK to PPO CLK and CLK to QERR CLK and CLK to QERR RESET to PPO RESET to QERR Parameter Min 410 1.2 -- -- 1 1 -- 0.5(5) 1.2(5) 1(5) -- -- Max. -- 1.9 2 3 4 4 1 1.8(5) 3(5) 2.4(5) 3 3 Unit MHz ns ns ns V/ns V/ns V/ns ns ns ns ns ns NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. 2. Includes 350ps of test load transmission line delay. 3. This parameter is not production tested. 4. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate). 5. For reference only. Final values to be determined. 12 IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST COMMERCIAL TEMPERATURE RANGE REGISTER TIMING RESET DCS CSR n n+1 n+2 n+3 n+4 CLK CLK tSU tH D1 - D25 tPD CLK to Q Q1 - Q25 tSU tH PAR_IN tPD CLK to Q PPO tPD CLK to QERR tPD CLK to QERR QERR Timing Diagram for SSTUA32866 Used as a Single Device; C0 = 0, C1 = 0 13 IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST COMMERCIAL TEMPERATURE RANGE REGISTER TIMING RESET DCS CSR n n+1 n+2 n+3 n+4 CLK CLK tSU tH D1 - D14 tPD CLK to Q Q1 - Q14 tSU tH PAR_IN tPD CLK to PPO PPO tPD CLK to QERR tPD CLK to QERR QERR (not used) Timing Diagram for the First SSTUA32866 (1:2 Register-A Configuration) Device Used in a Pair; C0 = 0, C1 = 1 14 IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST COMMERCIAL TEMPERATURE RANGE REGISTER TIMING RESET DCS CSR n n+1 n+2 n+3 n+4 CLK CLK tSU tH D1 - D14 tPD CLK to Q Q1 - Q14 tSU tH PAR_IN (1) tPD CLK to PPO PPO (not used) QERR tPD CLK to QERR tPD CLK to QERR Timing Diagram for the First SSTUA32866 (1:2 Register-B Configuration) Device Used in a Pair; C0 = 1, C1 = 1 15 IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST COMMERCIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS (VDD = 1.8V 0.1V) VDD DUT TL = 50 CLK Inputs CLK CLK Test Point RL = 100 Test Point LVCMOS RESET Input tINACT IDD 10% VDD VDD/2 VDD/2 0V tACT 90% Output CLK CLK tPLH VTT VICR Out CL = 30 pF TL = 350ps, 50 RL = 1K Test Point RL = 1K Load Circuit VICR tPHL VID VOH VTT VOL Voltage and Current Waveforms Inputs Active and Inactive Times tW Input VICR VICR VID Voltage Waveforms - Propagation Delay Times Voltage Waveforms - Pulse Duration LVCMOS RESET Input VIH VDD/2 VIL tRPHL VOH Output CLK VICR CLK tSU Input VREF tH VIH VREF VIL VID VTT VOL Voltage Waveforms - Propagation Delay Times Voltage Waveforms - Setup and Hold Times NOTES: 1. CL includes probe and jig capacitance. 2. IDD tested with clock and data inputs held at VDD or GND, and IO = 0mA 3. All input pulses are supplied by generators having the following characteristics: PRR 10MHz, ZO = 50, input slew rate = 1 V/ns 20% (unless otherwise specified). 4. The outputs are measured one at a time with one transition per measurement. 5. VTT = VREF = VDD/2 6. VIH = VREF + 250mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input. 7. VIL = VREF - 250mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input. 8. VID = 600mV. 9. tPLH and tPHL are the same as tPDM. 16 IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST COMMERCIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS (VDD = 1.8V 0.1V) VDD DUT Out RL = 50 Test Point CL = 10 pF Load Circuit: High-to-Low Slew-Rate Adjustment Output 80% VOH 20% dv_f dt_f VOL Voltage Waveforms: High-to-Low Slew-Rate Adjustment DUT Out CL = 10 pF Test Point RL = 50 Load Circuit: Low-to-High Slew-Rate Adjustment dt_r dv_r 80% VOH 20% Output VOL Voltage Waveforms: Low-to-High Slew-Rate Adjustment NOTES: 1. CL includes probe and jig capacitance. 2. All input pulses are supplied by generators having the following characteristics: PRR 10MHz, ZO = 50, input slew rate = 1 V/ns 20% (unless otherwise specified). 17 IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST COMMERCIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS (VDD = 1.8V 0.1V) VDD Timing Inputs RL = 1K tPLH Test Point Output Waveform 2 VOH 0.15V 0V VICR VICR VI(PP) DUT Out CL = 10 pF Voltage Waveforms - Open-Drain Output LOW-to-HIGH Transition Time with Respect to Clock Inputs Load Circuit: QERR Output DUT Out CL = 5 pF Test Point RL = 1K CK CK tPLH Output VICR tPLH VICR VI(PP) VOH VTT VOL Load Circuit: Partial-Parity-Out Load Circuit Voltage Waveforms - Propagation Delay Times with with Respect to Clock Inputs LVCMOS RESET LVCMOS RESET Input tPLH Output Waveform 2 VOH 0.15V 0V Output VOH VTT VOL VCC VCC/2 0V VIH Input VDD/2 VIL tPLH Voltage Waveforms - Open-Drain Output LOW-to-HIGH Transition Time with Respect to Reset Input Voltage Waveforms - Propagation Delay Times with with Respect to Reset Input Timing Inputs tPLH Output Waveform 1 VICR VICR VI(PP) VCC VCC/2 VOL Voltage Waveforms - Open-Drain Output HIGH-to-LOW Transition Time with Respect to Clock Inputs NOTES: 1. CL includes probe and jig capacitance. 2. All input pulses are supplied by generators having the following characteristics: PRR 10MHz, ZO = 50, input slew rate = 1 V/ns 20% (unless otherwise specified). 18 IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XX XXX XX SSTUA32 Temp. Range Device Type Package BFG Low Profile, Fine Pitch, Ball Grid Array - Green 866 1.8V Configurable Registered Buffer with Address-Parity Test 0C to +70C 74 CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com 19 |
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